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| MC100LVEL14 3.3V ECL 1:5 Clock Distribution Chip Description The MC100LVEL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of -3.0 V to -3.8 V ( or 3.0 V to 3.8 V). The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Features http://onsemi.com MARKING DIAGRAM 20 20 1 100LVEL14 AWLYYWWG SOIC-20 DW SUFFIX CASE 751D 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. * * * * * * * 50 ps Output-to-Output Skew Synchronous Enable/Disable Multiplexed Clock Input ESD Protection: Human Body Model >2 kV The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V Internal Input Pulldown Resistors on CLK * * Q Output will Default LOW with Inputs Open or at VEE * Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test * Moisture Sensitivity Level 1 * * * Pb-Free Packages are Available* For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V-0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 303 devices *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2006 November, 2006 - Rev. 8 1 Publication Order Number: MC100LVEL14/D MC100LVEL14 VCC 20 EN 19 VCC NC SCLK CLK CLK VBB SEL VEE 18 17 16 15 10 D Q 14 13 12 11 Table 1. PIN DESCRIPTION PIN CLK, CLK SCLK EN SEL Q0-4, Q0-4 FUNCTION ECL Diff Clock Inputs ECL Scan Clock Input ECL Sync Enable ECL Clock Select Input ECL Diff Clock Outputs Reference Voltage Output Positive Supply Negative Supply No Connect 1 Q0 2 Q0 3 Q1 4 Q1 5 Q2 6 Q2 7 Q3 8 Q3 9 Q4 10 Q4 VBB VCC VEE NC Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout (Top View) and Logic Diagram Table 2. FUNCTION TABLE CLK L H X X X SCLK X X L H X SEL L L H H X EN L L L L H Q L H L H L* *On next negative transition of CLK or SCLK X = Don't Care Table 3. MAXIMUM RATINGS Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder Pb Pb-Free 0 lfpm 500 lfpm Standard Board <2 to 3 sec @ 248C <2 to 3 sec @ 260C SOIC-20 SOIC-20 SOIC-20 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI v VCC VI w VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 -6 to 0 50 100 0.5 -40 to +85 -65 to +150 90 60 30 to 35 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 2 MC100LVEL14 Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 1) -40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 2) Output LOW Voltage (Note 2) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) VPP < 500 mV VPP y 500 mV Input HIGH Current Input LOW Current Others CLK 0.5 -300 2215 1470 2135 1490 1.92 Min Typ 32 2295 1605 Max 40 2420 1745 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 25C Typ 32 2345 1595 Max 40 2420 1680 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 85C Typ 34 2345 1595 Max 42 2420 1680 2420 1825 2.04 Unit mA mV mV mV mV V 1.3 1.5 2.9 2.9 150 1.2 1.4 2.9 2.9 150 1.2 1.4 2.9 2.9 150 V V mA mA mA IIH IIL 0.5 -300 0.5 -300 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 2. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V. Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.3 V (Note 4) -40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 5) Output LOW Voltage (Note 5) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 6) VPP < 500 mV VPP y 500 mV Input HIGH Current Input LOW Current Others CLK 0.5 -300 -1085 -1830 -1165 -1810 -1.38 Min Typ 32 -1005 -1695 Max 40 -880 -1555 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 25C Typ 32 -955 -1705 Max 40 -880 -1620 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 85C Typ 34 -955 -1705 Max 42 -880 -1620 -880 -1475 -1.26 Unit mA mV mV mV mV V -2.0 -1.8 -0.4 -0.4 150 -2.1 -1.9 -0.4 -0.4 150 -2.1 -1.9 -0.4 -0.4 150 V V mA mA mA IIH IIL 0.5 -300 0.5 -300 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 5. Outputs are terminated through a 50 W resistor to VCC - 2.0 V. 6. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V. http://onsemi.com 3 MC100LVEL14 Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.3 V (Note 7) -40C Symbol fmax tPLH tPHL tSKEW tJITTER tS tH VPP tr tf Characteristic Maximum Toggle Frequency (Figure 2) Prop Delay Part-to-Part Skew Within-Device Skew (Note 8) Random Clock Jitter (RMS) @ 1 GHz (Figure 2) Setup Time EN Hold Time EN Input Swing CLK (Note 9) Output Rise/Fall Times Q (20% - 80%) 0 250 150 230 0.2 -95 150 1000 500 CLK to Q (Diff) CLK to Q (SE) SCLK to Q 520 470 470 Min Typ >1 720 770 770 200 50 <1 0 250 150 230 0.2 -110 160 1000 500 580 530 530 Max Min 25C Typ >1 680 680 680 780 830 830 200 50 <1 0 250 150 230 0.2 -125 175 1000 500 630 580 580 Max Min 85C Typ >1 830 880 880 200 50 <1 Max Unit GHz ps ps ps ps ps mV ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. VEE can vary 0.3 V. 8. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 9. VPP(min) is minimum input swing for which AC parameters guaranteed. 900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 (JITTER) 9 8 7 6 5 4 3 2 1 1500 1800 2100 2400 JITTER OUT ps (RMS) 0 300 600 900 1200 FREQUENCY (MHz) Figure 2. Fmax/Jitter http://onsemi.com 4 EE EE EEEEEEEEE EEEEEEEEE EEEEEEEEE MC100LVEL14 Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device VTT VTT = VCC - 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEL14DW MC100LVEL14DWG MC100LVEL14DWR2 MC100LVEL14DWR2G Package SOIC-20 SOIC-20 (Pb-Free) SOIC-20 SOIC-20 (Pb-Free) Shipping 38 Units / Rail 38 Units / Rail 1000 Tape & Reel 1000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices http://onsemi.com 5 MC100LVEL14 PACKAGE DIMENSIONS SOIC-20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE G D A 11 X 45 _ q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_ H M B M 20 10X 0.25 E 1 10 20X B 0.25 M B TA S B S A e SEATING PLANE h 18X A1 T C ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative L http://onsemi.com 6 MC100LVEL14/D |
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